One of the most popular approaches for realizing analog signal processing in CMOS integrated circuits is through the use of a switched-capacitor circuit which operates as a discrete-time signal processor. As one typical circuit example thereof, there is a sample-and-hold amplifier shown in FIG. 8. This circuit has a structure shown in many books for reference, including “Analog MOS Integrated Circuits for Signal Processing” written by Rubik Gregorian, Gabor C. Temes published by A Wiley-interscience Publication (John Wiley & Sons, Inc.) pp 416-417 (1986). This sample-and-hold amplifier is composed of an inverter (inverting amplifier) 1 with open-loop gain G1, a switch SW1 provided between an input and an output of the inverter, a feedback capacitor CF whose one end is connected to an inverter input terminal Ain, and a switch SW2 which is connected to the other end of the feedback capacitor CF and selectively connects the feedback capacitor to an input terminal for providing an input voltage Vin or an inverter output terminal Aout. The inverter output terminal Aout is directly connected to an output terminal for providing an output voltage Vout.
The sample-and-hold amplifier operates in two-phases of a sampling phase and an amplification phase. During the sampling phase, the sample-and-hold amplifier is in a state of FIG. 8A, in which the switch SW1 is in an ON-state, the switch SW2 is connected to the input signal voltage Vin, and the signal voltage Vin is sampled in the feedback capacitor CF. During the amplification phase, as shown in FIG. 8B, the each switch is turned into the inversion state from those on the sampling phase respectively, and the feedback capacitor CF is connected between the input and output of the inverter, and then, the output signal voltage Vout is obtained. The output signal voltage Vout at this time comes to Vout=Vin for the following reason when the open-loop gain G1 of the inverter 1 is sufficiently high.
Given that the open-loop gain of the inverter is G1, a feedback loop is formed between the input and output of the inverter during both the sampling phase and the amplification phase, the deviation of input voltage at the inverter input terminal Ain comes to 1/G1 with respect to the deviation of output voltage Vout. Accordingly, when G1 is extremely high, the voltage of the amplifier input terminal Ain hardly changes, which can be considered as a so-called “virtual ground state”. In this way, when the voltage at the inverter input terminal Ain does not change, the voltage at the other end of the capacitor does not change, which comes to Vout=Vin, because the electric charge in the capacitor CF is conserved in accordance with the charge conservation law. Accordingly, the input voltage Vin sampled on the sampling phase is held as the inverter output in the following amplification phase. This type of sample-and-hold amplifier has the feature that it is possible to obtain an output signal which is free of the influence of a threshold voltage or an offset voltage of the inverter.
Next, one example in which the inverter 1 of FIG. 8 is replaced with a concrete structure is shown in FIG. 9. The inverter 1 is composed of a common source (source-grounded) NMOS (Negative channel Metal Oxide Semiconductor) input transistor M1 whose gate serves as the inverter input terminal Ain, a PMOS (Positive channel Metal Oxide Semiconductor) load transistor M2 operating as a constant current source whose gate is connected to a bias voltage Vbp1, an NMOS transistor M3 cascode-connected to the NMOS transistor M1, in which a bias voltage Vbn2 is applied to its gate, and a PMOS transistor M4 cascode-connected to the PMOS transistor M2, in which the bias voltage Vbp2 is applied to its gate. The transistors M3 and M4 are provided in order to increase the drain resistances of the transistors M1 and M2, respectively, and not essential components for the inverter. However, the transistors M3 and M4 are generally used in a CMOS analog circuit in order to raise the gain of the inverter.